<!doctype html><html lang=en><head><meta charset=utf-8><meta name=viewport content="width=device-width,initial-scale=1,viewport-fit=cover"><base href=https://www.lowrisc.org><link rel=icon type=image/png sizes=32x32 href=/favicon.png><title>Rocket core overview &middot; lowRISC: Collaborative open silicon engineering</title><link href=/main.21c9d.css rel=stylesheet><script type=application/javascript>var doNotTrack=false;if(!doNotTrack){(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)})(window,document,'script','https://www.google-analytics.com/analytics.js','ga');ga('create','UA-53520714-1','auto');ga('send','pageview');}</script></head><body><header><nav class="navbar navbar-expand-md navbar-light"><div class=container><a class=navbar-brand href=#><img src=/img/logo/logo-dualcolor.svg alt=lowRISC></a>
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<span class=navbar-toggler-icon></span></button><div class="collapse navbar-collapse" id=navbarCollapse><ul class="navbar-nav ml-auto"><li class=nav-item><a href=/our-work class=nav-link>Our work</a></li><li class=nav-item><a href=/open-silicon class=nav-link>Open Silicon</a></li><li class=nav-item><a href=/community class=nav-link>Community</a></li><li class=nav-item><a href=/blog class=nav-link>Blog</a></li><li class=nav-item><a href=/jobs class=nav-link>Jobs</a></li><li class=nav-item><a href=/about class=nav-link>About us</a></li><li class=nav-item><a class="btn lr-navbar-btn-gh" href=https://github.com/lowrisc>GitHub</a></li></ul></div></div></nav></header><main role=main><div class=container><h1>Rocket core overview</h1><p>The Rocket core is an in-order scalar processor that provides a
5-stage pipeline. It implements the RV64G variant of the RISC-V
ISA. The Rocket core has one integer ALU and an optional FPU. An
accelerator or co-processor interface, called RoCC, is also provided.</p><p>Further details of the RISC-V Rocket core pipeline can be found
<a href=http://www-inst.eecs.berkeley.edu/~cs250/fa13/handouts/lab2-riscv.pdf#13>here</a>. See
p.13 of this document for a detailed diagram of Rocket&rsquo;s
microarchitecture. The Rocket core is sometimes described as a 6-stage
pipeline with the addition of a <code>pcgen</code> stage. While it is useful to
layout the figure in this way, the stage is perhaps best considered as
part of the other stages and is not a distinct pipeline stage in the
traditional sense.</p><p>The <code>pcgen</code> and <code>fetch</code> stages are shown below. Instruction fetch is
assisted by a gshare predictor, Return Address Stack (RAS) and Branch
Target Buffer (BTB).</p><p><img src=../figures/icache.png alt=Drawing style=width:500px></p><p>The remaining four pipeline stages are shown below:</p><p><img src=../figures/pipeline.png alt=Drawing style=width:550px></p><p>The L1 data cache (original, without MMIO) is shown below.</p><p><img src=../figures/dcache.png alt=Drawing style=width:650px></p><p>Note: The data cache&rsquo;s metadata (tags etc.) and data arrays are shown in
both stage 1 (for read operations) and stage 4 (for write operations).</p><p>Key:</p><ul><li>amoalu: Atomic memory operation ALU</li><li>mshrs: Miss status handling registers</li><li>prober: Handles incoming probe requests (i.e. tag lookups or requests to revoke permissions)</li><li>code: placeholder for ECC support</li></ul></div></main><footer class=lr-footer><div class=container><div class=row><div class="col-lg-2 d-none d-lg-block"><img src=/img/logo/logo-dualcolor.svg width=150px></div><div class=col><p>The text content on this website is licensed under a <a href=https://creativecommons.org/licenses/by/4.0/>Creative Commons Attribution 4.0 International License</a>, except where otherwise noted. No license is granted for logos or other trademarks. Other content &copy; lowRISC Contributors.</p><a href=/privacy-policy>Privacy and cookies policy</a>
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